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| STSR2 FORWARD SYNCHRONOUS RECTIFIERS SMART DRIVER s s s s s s SUPPLY VOLTAGE RANGE: 4.5V TO 5.5V TYPICAL PEAK OUTPUT CURRENT: SOURCE -2A, SINK 3.5A OPERATING FREQUENCY: 20 TO 750 KHZ SMART TURN-OFF ANTICIPATION TIMING OPERATION INDEPENDENT FROM THE FORWARD MAGNETIC RESET TECHNIQUE POSSIBILITY TO OPERATE IN DISCONTINUOUS MODE SO-8 DESCRIPTION STSR2 Smart Driver IC provides two complementary high current outputs to drive Power Mosfets. The IC is dedicated to properly drive secondary Synchronous Rectifiers in medium power, low output voltage, high efficiency Forward Converters. From a synchronizing clock input, STSR2 generates two driving signals with the self-setting of dead time between complementary pulses. The IC operation prevents secondary side shoot-through conditions providing proper timing at the outputs turn-off transition. This smart function operates through a fast cycle-after-cycle control logic mechanism based on an internal high frequency oscillator, synchronized by the clock signal. A fixed anticipation in turning-off the OUT GATE1 with respect to the clock signal transition is provided, SCHEMATIC DIAGRAM Vcc 2 while the anticipation in turning off the OUTGATE2 can be set through external components. The adopted transitions revelation mechanism makes circuit operation independent by the forward magnetic reset technique used, avoiding most of the common problems inherent in self-driven synchronous rectifiers. A special Inhibit function allows the shut-off of OUTGATE2. This feature makes discontinuous conduction mode possible and prevents the freewheeling mosfet from sinking current from the output. STSR2 automatically turns off the outputs when duty-cycle is lower than 13%, while STSR2M works even at very low duty-cycle values. + BIAS UVLO 5.7V CK 4 PEAK DETECTOR ANTICIPATION SET 3 SETANT2 + + HIGH FREQUENCY OSCILLATOR 1 OUTGate1 DIGITAL CONTROL OUTPUT BUFFERS 7 OUTGate2 INHIBIT 5 + 25mV 6 8 SGLGND PWRGND October 2002 1/11 STSR2 ABSOLUTE MAXIMUM RATINGS Symbol VCC VINHIBIT VCK ILX PTOT ESD Tstg Top DC Input Voltage Max INHIBIT Voltage (*) Clock Input Voltage Range (*) Switching Peak Current Continuous Power Dissipation at TA=105C without heatsink Human Body Model Pins 1,,2, 4, 5, 6, 7, 8 Pin 3 Storage Temperature Range Operating Junction Temperature Range Parameter Value -0.3 to 6 -0.3 to VCC -0.6 to VCC -0.3 to VCC 2 270 1 0.9 -55 to +150 -40 to +125 Unit V V V V A mW KV KV C C VOUTGATE Max Gate Drive Output Voltage Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. (*) A higher positive voltage level can be applied to the pin with a resistor which limits the current flowing into the pin to 10mA maximum THERMAL DATA Symbol Rthj-amb Rthj-amb Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient (*) SO-8 40 160 Unit C/W C/W (*) This value is referred to one layer pcb board with minimum copper connections for the leads. a minimum value of 120 C/W can be obtained improving thermal conductivity of the board ORDERING CODES TYPE STSR2 STSR2M SO-8 STSR2CD STSR2MCD SO-8 (T&R) STSR2CD-TR STSR2MCD-TR CONNECTION DIAGRAM (top view) 2/11 STSR2 PIN DESCRIPTION Pin N 1 2 Symbol OUTGATE1 VCC Name and Function Gate Drive signal for Rectifier MOSFET. Anticipation (tANT1) in turning off OUTGATE1 is provided when the clock input goes to low level. The supply voltage range from 4.5V to 5.5V allows applications with logic gate threshold mosfets. UVLO feature guarantees proper start-up while it avoids undesirable driving during eventual dropping of the supply voltage. The voltage on this pin sets the anticipation (tANT1) in turning off the OUTGATE2. It is possible to choose among three different anticipation times by discrete partitioning of the supply voltage. This input provides synchronization for IC's operations, being the transitions between the two output conditions based on a positive threshold, equal for the two slopes. A smart internal control logic mechanism using a 15MHz internal oscillator generates proper anticipation timing at the turn-off of each output. This feature allows safe turn-off of Synchronous Rectifiers avoiding any eventual shoot-through situation on secondary side at both transitions. Smart clock revelation mechanism makes these operations independent by false triggering pulses generated in light load conditions and by particular demagnetization techniques.Absolute maximum voltage rating of the pin can be exceeded limiting the current flowing into the pin to 10mA max. This input enables OUTGATE2 to work when its voltage is lower than the negative threshold voltage (VINHIBIT 3 SETANT2 4 CK 5 INHIBIT 6 7 8 SGLGND OUTGATE2 PWRGND 3/11 STSR2 ELECTRICAL CHARACTERISTICS (VCC=5V, CK= 250kHz, VINHIBIT =-200mV, TJ =-40 to 125C, unless otherwise specified.) Symbol Parameter Test Conditions Min. Typ. 3.8 3.5 CK=0V CK=0V GATE DRIVER OUTPUTS VOL Output Low Voltage VOH IOUT Output High Voltage Output Source Peak Current Output Sink Peak Current Output Series Source Resistance Output Series Sink Resistance OUTGATE1,2 Rise Time OUTGATE1,2 Fall Time IZ = 2mA OUTGATE1,2= no load 5.5 3.6 5.8 22 3 0.10 4.70 4.85 2 3.5 0.75 0.5 40 30 130 50 6 30 5 0.16 V V A Max. 4 Unit V V V mA SUPPLY INPUT AND UNDER VOLTAGE LOCK OUT VCCON Start Threshold VCCOFF VZ ICC Turn OFF Threshold After Start Zener Voltage Unloaded Supply Current OUTGATE1,2= no load IOUTGATE1,2=-200mA IOUTGATE1,2=200mA ROUT IOUTGATE1,2=-200mA IOUTGATE1,2=200mA CLOAD=5nF (Note 1) CLOAD=5nF (Note 1) 1.5 0.8 tR tF tP1 tP2 ns ns ns ns Clock Propagation Delay to No Load Turn ON of OUTGATE1 Clock Propagation Delay to No Load Turn ON of OUTGATE2 No Load VANT2 = 0 to 1/3VCC; no load VANT2 = 1/3VCC to 2/3VCC; no load VANT2 = 2/3VCC to VCC; no load -0.1 TJ = 25C VINHIBIT = 200mV VINHIBIT = -200mV VINHIBIT = 200mVNo Load TJ = 25C TJ = 25C TJ = 25C STSR2M for STSR2 for STSR2 13 -30 TURN-OFF ANTICIPATION TIME OUTGATE1 Turn-off tANT1 Anticipation Time OUTGATE2 Turn-off tANT2 Anticipation Time 20 75 150 225 0.1 -25 -400 1 250 2.6 14 18 20 200 2.8 600 ns ns ISETANT2 VH IH Leakage Current (Note 2) Threshold Voltage Leakage Current (Note 2) A mV nA A ns V A % INHIBIT OUTGATE2 ENABLE tON(GATE2) OUTGATE1 Turn-off Anticipation Time Reference Voltage VCK ICK DOFF LX Leakage Current Duty Cycle Shut Down Duty Cycle Turn ON after Shut Down Minimum Pulse Width tPW ns Note1: tR is measured between 10% and 90% of the final voltage; tF is measurerd between 90% and 10% on the initiual voltage Note2: Parameter guaranteed by design 4/11 STSR2 TIMING DIAGRAM APPLICATION INFORMATION : STSR2 IN FORWARD CONVERTER SECONDARY SIDE Feedback Loop TRANSFORMER INDUCTOR Vin MosfetN Q2 Cout Vout MosfetN Q1 1 8 7 100nF +5V 2 PWM OUTGate1 OUTGate2 PWRGND Vcc 100nF R1 6 SGLGND STSR2 INHIBIT 5 SETANT 3 R2 R3 Ck 4 R4 +5V D3 R5 D1 D2 option +5V NOTES 1) Ceramic Capacitors C1 and C2 must be placed very close to the IC; 2) R1 and R2 set the anticipation time by partitioning the Vcc voltage; 3) R3 and R4 is a resistor divider meant to provide the correct Ck voltage range; 4) R5 limits the current flowing through diode D2 when Freewheeling drain voltage is high; 5) D1 could be necessary to protect INHIBIT pin from negative voltages. 6) D2 could be necessary to protect INHIBIT pin from voltages higher than Vcc 7) D3 could be necessary to protect CK pin from voltages higher than Vcc. 8) SGLGND layout trace must not include OUTGATE1,2 current paths. 9) A capacitor in parallel with R4 could be necessary to eliminate turn off voltage spike. 5/11 STSR2 EXAMPLE OF COMPONENTS SELECTION FOR A FORWARD CONVERTER Forward Specification: VIN=36-72V VOUT=3.3V n=Np/Ns=4.5 R3 and R4 are calculated assuring a minimum voltage of 2.8V at Ck pin. At 36V input, the voltage on the secondary winding is 36/4.5=8V. Choosing R3=1.5K, R4 results to be: V CK + I CK ( 2.8 ) x R 3 2.8V + 220A x 1.5 k R 4 --------------------------------------------------------------- = 1k x ------------------------------------------------------------------------- = 965 8 V - 220A x 1.5 k - 2.8V V IN - I CK ( 2.8 ) x R 3 - V CK R4=1k is chosen. At 72V input the current at Ck pin is calculated as: V IN ( max ) - V CC - 0.3 16 - 5 - 0.3 I CK = ---------------------------------------------------- = ----------------------------- = 7.13mA R3 1.5k This value is below the maximum allowable current flowing into the Ck pin (10mA). If the 10mA value is exceeded an external diode connected to VCC must be added (D3). R1 and R 2 values set the anticipation time for OUTGATE2. For R1= and R2=0, tANT2=75ns; for R1=R 2=10k, tANT2=150ns; for R 1=0 and R2=, tANT2=225ns. The RC group composed by R5 and the parasitic capacitance of Inhibit pin (typically 5pF) delays the signal on Inhibit comparator. This delay must be lower than 200ns. This condition imposes a maximum value for R5 of about 20k. In general a suggested value for R5 is 10k. At 72V input, the secondary voltage is 16V, so the maximum current flowing into Inhibit pin is 16V/10k=1.6mA which is below the maximum allowable current for the pin (10mA). If the 10mA value is exceeded an external diode (D2) connected to VCC must be added. The maximum negative voltage of -0.6V must be guaranteed for the Inhibit pin. If this negative voltage is exceeded the current must be limited to 50mA. If necessary, a diode (D1) connected to SGLGND can be added to satisfy this specification. INHIBIT OPERATION OF OUTGATE2 IN DISCONTINUOUS CONDUCTION MODE 6/11 STSR2 INHIBIT OPERATION OF OUTGATE2 NOTE: VINHIBIT =+200mV 7/11 STSR2 TYPICAL PERFORMANCE CHARACTERISTICS (unless otherwise specified Tj = 25C Figure 1 : Zener Characteristics Figure 4 : Sink-Source ON Resistance vs Temperature Figure 2 : Rise and Fall Time vs Load Capacitor Figure 5 : Clock Threshold Voltage vs Temperature Figure 3 : OUTGATE1,2 vs Characteristics Figure 6 : INHIBIT Threshold Voltage vs Temperature 8/11 STSR2 Figure 7 : Supply Current vs Load Capacitor (each output) Figure 10 : Duty Cycle Shut Down vs Temperature Figure 8 : Supply Current vs Clock Frequency Figure 11 : Duty Cycle Turn ON After Shut Down vs Temperature Figure 9 : TON(GATE2) vs Temperature Figure 12 : Clock Leakage Current vs Clock Voltage 9/11 STSR2 SO-8 MECHANICAL DATA DIM. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.149 0.015 5.0 6.2 0.65 0.35 0.19 0.25 0.1 mm. MIN. TYP MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 0.189 0.228 0.050 0.150 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. MAX. 0.068 0.009 0.064 0.033 0.018 0.010 0.019 0016023 10/11 STSR2 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com 11/11 |
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